| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a memory control device and method capable of executing an auto-refresh cycle and a memory cycle for SRAM in parallel by sharing an address bus and a data bus for SDRAM and SRAM. <P>SOLUTION: When a host controller 100 instructs execution of the memory cycle of the SRAM 320 to a memory controller 200, an SRAM controller 203 in the memory controller 200 outputs a memory control command for the SRAM 320 to an SRAM control line 504, and outputs address data through a shared address/data bus 503. At the same time, an SDRAM controller 202 which has received a refresh trigger from a refresh counter 201 outputs a refresh command to the SDRAM 310 through an SDRAM control line 501 and an SDRAM exclusive address signal line 502. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
