| 摘要 |
PROBLEM TO BE SOLVED: To provide a pulse signal processing circuit capable of effectively suppressing a defect caused in an output PWM signal due to unevenness of operating characteristics of a pair of active elements in the case of delivering a PWM signal through a PWM signal output section including a pair of the active elements as the output PWM signal. SOLUTION: The pulse signal processing circuit is provided with: the PWM signal output section 28 including a MOS-FET 31 the gate of which receives a PWM signal through a delay section 26, a MOS-FET 32 the gate of which receives the PWM signal through a delay section 27, and a common output terminal 33 formed by interconnecting drains of the MOS-FETs 31, 32; an attached circuit section 22 for detecting an average voltage at the common output terminal 33; and a control signal forming section 29 for forming a control signal in response to the detected average voltage and adjusting either or both of a signal delay time in the delay section 26 and a signal delay time in the delay section 27 in response to the control signal. COPYRIGHT: (C)2005,JPO&NCIPI
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