发明名称 |
PROGRAMMABLE LOGIC DEVICE AND DESIGNING METHOD THEREOF |
摘要 |
PROBLEM TO BE SOLVED: To permit the reduction of the power consumption and the area of a programmable logic device consisting of programmable logical elements. SOLUTION: The programmable logic device 101 consisting of programmable logical elements is provided with a first logical element 102, and a second logical element 104 having the same logic as the first logical element 102 with the lower operating speed in the upper limit of designing compared with that of the first logical element 102. COPYRIGHT: (C)2005,JPO&NCIPI
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申请公布号 |
JP2005268536(A) |
申请公布日期 |
2005.09.29 |
申请号 |
JP20040078826 |
申请日期 |
2004.03.18 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
MORI ATSUHIRO;MARUI SHINICHI;OKAMOTO MINORU |
分类号 |
H01L21/8234;H01L21/82;H01L27/088;H01L27/118;(IPC1-7):H01L21/82;H01L21/823 |
主分类号 |
H01L21/8234 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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