发明名称 |
Padless structure design for easy identification of bridging defects in lines by passive voltage contrast |
摘要 |
A new test structure to locate bridging defects in a conductive layer of an integrated circuit device is achieved. The test structure comprises a line comprising a conductive layer overlying a substrate. The line is coupled to ground. A plurality of rectangles comprises the conductive layer. The rectangles are not connected to the line or to other rectangles. Near edges of the rectangles and of the line are parallel. The rectangles are floating. The test structure is used with a passive voltage contrast test in a scanning electron microscope. A test structure and method to measure critical dimensions is disclosed.
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申请公布号 |
US6949765(B2) |
申请公布日期 |
2005.09.27 |
申请号 |
US20020288193 |
申请日期 |
2002.11.05 |
申请人 |
CHARTERED SEMICONDUCTOR MANUFACTURING LTD. |
发明人 |
SONG ZHIGANG;REDKAR SHAILESH;OH CHONG KHIAM |
分类号 |
G01R31/311;H01L23/544;(IPC1-7):H01L23/58 |
主分类号 |
G01R31/311 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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