| 摘要 |
The invention relates to a non-volatile memory test structure, comprising a plurality of memory cells arranged in rows and columns, each memory cell comprising at least a memory transistor and having a source terminal, a gate terminal and a drain terminal. In order to provide a fast and effective test structure to be used for fast reliability evaluation in monitoring of non-volatile memory elements on every wafer it is proposed according to the present invention that:-a group of said memory cells is connected in parallel,-the source terminals of the memory cells in the group are connected together and to a source line,-the drain terminals of the memory cells in the group are connected together and to a drain line,-the gate terminals of the memory cells in the group are connected together and to a gate line, and-said gate line has two connections to apply an electrical current to said gate line for using it as a heating means.
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