| 摘要 |
Provided is a test mode circuit of a semiconductor device comprising: a test mode control unit for generating a test mode control signal which is decoded in response to a plurality of address codes corresponding to kinds of test modes, respectively; a multi-level generating unit for generating multi levels; a multi-level transfer unit for loading the multi levels on one multi-level test mode line in response to a control signal from the test mode control unit; and a multi-level identifying unit for identifying the multi levels to be inputted from the multi-level transfer unit, to supply a generated test signal to a test mode utilizing circuit.
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