发明名称 |
Low voltage pull-down circuit |
摘要 |
A low voltage pull-down circuit for maintaining a node at a logic LOW voltage is provided. When a logic LOW is desired, the circuit provides a low-impedance path from the node to ground. The node may be easily pulled-up to a logic HIGH voltage, for example, by simply removing the low-impedance path and allowing a voltage source to reach the node through a resistor or transistor.
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申请公布号 |
US6949965(B1) |
申请公布日期 |
2005.09.27 |
申请号 |
US20030726964 |
申请日期 |
2003.12.02 |
申请人 |
LINEAR TECHNOLOGY CORPORATION |
发明人 |
JURGILEWICZ ROBERT P.;FLEURY VICTOR F.;ZEMKE ROGER |
分类号 |
H03K5/22;H03K17/22;H03K17/30;H03L7/00;(IPC1-7):H03L7/00 |
主分类号 |
H03K5/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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