发明名称 |
System and method for facilitating efficient application of logical configuration information in VLSI circuit analysis tools |
摘要 |
A method for optimizing relationships between logic commands defining a circuit design input to an analysis tool is described. The method comprises, responsive to a determination that a value of logic level of a signal can be inferred and responsive to an attempt by the analysis tool to set the logic level of the signal to a calculated value, determining whether the calculated value is equal to the inferred value; and if the calculated value is equal to the inferred value, setting the logic level of the signal to the inferred value.
|
申请公布号 |
US2005210427(A1) |
申请公布日期 |
2005.09.22 |
申请号 |
US20040803692 |
申请日期 |
2004.03.18 |
申请人 |
KELLER S B;ROGERS GREGORY D;ROBBERT GEORGE H |
发明人 |
KELLER S. B.;ROGERS GREGORY D.;ROBBERT GEORGE H. |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|