发明名称 |
Semiconductor device that enables simultaneous read and write/read operation |
摘要 |
A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.
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申请公布号 |
US2005207247(A1) |
申请公布日期 |
2005.09.22 |
申请号 |
US20050125073 |
申请日期 |
2005.05.10 |
申请人 |
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发明人 |
HONDA YASUHIKO;KATO HIDEO;SAITO HIDETOSHI;KURIYAMA MASAO;HARA TOKUMASA;IKEDA TAKAFUMI;HIRAMATSU TATSUYA |
分类号 |
G11C16/00;G11C5/00;G11C8/12;G11C16/10;G11C16/26;(IPC1-7):G11C5/00 |
主分类号 |
G11C16/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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