| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock layout system and method capable of designing layout while evaluating the level of congestion due to buffer insertion, so that flip-flops are evenly placed. SOLUTION: The clock layout system includes an F/F identifying part 12b that identifies flip-flops among cells placed in the design area of a logic circuit; a cut-line setting part 12c that divides the design area by means of a first segment; an F/F relocating part 12d that relocates the flip-flops so that the difference in number of flip flops between the divided areas is minimized; and a cell relocating part 12e that relocates the cells other than the flip-flops in the divided areas so that the number of wires crossing the first segment dividing the design area is minimized. COPYRIGHT: (C)2005,JPO&NCIPI
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