SEMICONDUCTOR MEMORY AND OPERATING METHOD OF SEMICONDUCTOR MEMORY

摘要

A bit line reset signal is supplied to the gate of an nMOS transistor (a precharge circuit) connecting a bit line to a precharge voltage line. The high level voltage of the bit line reset signal is kept at a first voltage during the precharge operation following a refresh operation, while it is kept at a second voltage, which is higher than the first voltage, during the precharge operation following an access operation. Thus, since the second voltage is not used during the precharge operation following the refresh operation, the consumed current of a circuit for generating the second voltage can be saved. In this way, particularly the consumed current (standby current) during a standby, in which internal refresh requests successively occur, can be saved.