发明名称 |
Calculating unit |
摘要 |
A calculating unit including a number of bit slices which is less than the number of positions of the operand to be processed. Each bit slice has a logic element and a communication bus between the logic element and the plurality of register cells. The register cells are connected in parallel with respect to the slice-internal communication bus and are controlled by a controller so that only one register cell of the plurality of register cells is coupled to the communication bus at a time.
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申请公布号 |
US2005210088(A1) |
申请公布日期 |
2005.09.22 |
申请号 |
US20050080998 |
申请日期 |
2005.03.14 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
JANSSEN NORBERT;ROEMER TANJA;SEDLAK HOLGER |
分类号 |
G06F7/00;G06F7/38;G06F7/48;G06F7/575;G06F9/302;H03K17/08;(IPC1-7):G06F7/00 |
主分类号 |
G06F7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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