| 摘要 |
<P>PROBLEM TO BE SOLVED: To control soft-error and latch-up of a semiconductor device. <P>SOLUTION: A p-well layer 9 and an n-well layer 15 are provided in parallel on the main surface of a p-type silicon substrate 1, and an STI8 is provided selectively to the surface area of the well layer. Moreover, a deep n-well layer 14 is selectively provided to the part just under the n-well layer 15 and to the bottom of the p-well layer 9 opposing to the region between STs 18 of the p-well layer 9, the deep n-well layer 14 is not provided to the bottom of the p-well layer 9 opposing to the ST18, and the bottom of the p-well layer 9 opposing to the STI8 is in contact with the p-type silicon substrate 1. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
