发明名称 |
TEST DEVICE AND TEST METHOD |
摘要 |
<p>A test device includes: a pattern generator for generating an address signal, a data signal, an expectation signal for supply to a memory under test; a logic comparator for outputting fail data when the output signal outputted from the memory under test does not coincide with the expectation signal; a first FBM for storing fail data in the first test; a second FBM for accumulating and storing the fail data stored in the first FBM and the fail data in a second test; and a remedy analysis unit for referencing the fail data stored in the first FBM and performing a defect remedy analysis of the memory under test. The first FBM accumulates and stores the fail data stored in the second FBM and fail data in a third test. The remedy analysis unit further references the fail data stored in the second FBM and performs a defect remedy analysis of the memory under test.</p> |
申请公布号 |
WO2005088645(A1) |
申请公布日期 |
2005.09.22 |
申请号 |
WO2005JP04010 |
申请日期 |
2005.03.08 |
申请人 |
ADVANTEST CORPORATION;FUJISAKI, KENICHI |
发明人 |
FUJISAKI, KENICHI |
分类号 |
G01R31/28;G11C29/00;G11C29/44;G11C29/56;(IPC1-7):G11C29/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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