发明名称 TEST METHOD AND CIRCUIT FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To sufficiently detect a failure of an interface part of a BIST design object circuit with a scan test design object circuit, and automatically generate a test pattern in a semiconductor integrated circuit using both a BIST and a scan test. <P>SOLUTION: In the semiconductor integrated circuit having both the BIST circuit 100 and the scan test design object circuit 120, a boundary scan circuit 101 is formed in the input and output terminal part of the BIST circuit 110 that becomes an interface with the scan test design object circuit 120, and the boundary scan circuit 101 is controlled so as to function as a part of a scan chain in a scan test of the scan test design object circuit 120, whereby the interface part of the BIST circuit 110 with the scan test design object circuit 120 is tested by use of the test pattern automatically generated by ATPG. <P>COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005257290(A) 申请公布日期 2005.09.22
申请号 JP20040065335 申请日期 2004.03.09
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 OZAWA NAOTO
分类号 G01R31/28;G06F11/22;H01L21/822;H01L27/04 主分类号 G01R31/28
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