| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device by which the EM-resistance property of a via plug is enhanced and a maximum current is made higher without enlarging a chip size. SOLUTION: The semiconductor device includes an underlayer wiring 21a, a second interlayer dielectric 22 on the underlayer wiring 21a, the via plug 23 which penetrates the second interlayer dielectric 22 and of which the bottom is connected to the underlayer wiring 21a, a plurality of dummy vias 24a to 24D which are arranged around the via plug 23 in the second interlayer dielectric 22 and shorter and smaller in diameter than the via plug 23, and an upper layer wiring 25 which is formed near a surface in the second interlayer dielectric 22 and in which the top of the via plug 23 and tops of the plurality of dummy vias 24a to 24d are connected to a termination portion. COPYRIGHT: (C)2005,JPO&NCIPI
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