| 摘要 |
The present invention provides a data processing apparatus and method for comparing first and second floating point operands to produce a comparison result. Each floating point operand has a sign component, an exponent component, and a fraction component. The data processing apparatus comprises first processing logic operable to receive, for each floating point operand, a first component derived from a predetermined number of most significant bits of the fraction component of that floating point operand, the predetermined number being less than the total number of bits constituting the fraction component. The first processing logic is further operable to receive the sign components and the exponent components of the first and second floating point operands and to compare the sign components, the exponent components and the first components of the first and second floating point operands in order to produce a plurality of signals indicative of the comparison. Evaluation logic is then used to evaluate whether the comparison result can be determined from those plurality of signals, and if so, the comparison result is determined. Further, second processing logic is provided which is operable, in the event that the evaluation logic determines that the comparison result cannot be determined from the plurality of signals, to receive, for each floating point operand, a second component derived from at least the bits of the fraction component of that floating point operand other than the predetermined number of most significant bits. The second processing logic then compares the second components of the first and second floating point operands in order to produce at least one further signal indicative of the comparison, and the evaluation logic is further operable to determine the comparison result from the plurality of signals and the at least one further signal. This technique provides a particularly quick and power efficient technique for producing the comparison result.
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