发明名称 POINTER INTERPRETATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To cut down the development period in an AU pointer interpretation function or the like redeveloped for extending a data band corresponding to a time cycle of several years and to cut down its development cost. SOLUTION: A pointer interpretation circuit is equipped with a plurality of pointer interpretation modules 870 to 873 each corresponding to given data band, a program memory 824 for storing a program for controlling behavior of a plurality of the modules, and inter-module communication ports 874 to 879 for transmitting and receiving necessary information between the plurality of the modules. As a means for speeding up a state judgment process for realizing real-time performing ability required for H1 bytes, H2 bytes that arrive every 125μsec, each module can be equipped with an H1, H2 byte decoder in which state judgment is possible only with reference to estimation results upon a software program through decoding beforehand an estimation condition estimated at the time of performing state transition judgment by a hardware process. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005260815(A) 申请公布日期 2005.09.22
申请号 JP20040072638 申请日期 2004.03.15
申请人 NEC ENGINEERING LTD 发明人 SHIMURA NAOKI
分类号 H04J3/00;(IPC1-7):H04J3/00 主分类号 H04J3/00
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