| 摘要 |
PROBLEM TO BE SOLVED: To provide an information processing board for reducing a load on an MPU due to bus right control or interruption since a conventional information processing board has a problem that the MPU controls local buses and a PCI bus so as to enlarge the load on the MPU and to further increase the load of the MPU when the interruption from an external peripheral device such as a LAN is frequently performed. SOLUTION: The board comprises: a north bus 210 being a first local bus to which the MPU 201 is connected; and a south bus 211 being a second local bus to which the external peripheral apparatus such as the LAN is connected. The north bus 210 and the south bus 211 are connected or unconnected by a gate 205. In the board, an FPGA 206 connected to the south bus 211 controls the connection/unconnection of the gate 205, controls the management and granting of south bus right, and generally controls the interruption with respect to the MPU 201 from the external peripheral devices. COPYRIGHT: (C)2005,JPO&NCIPI
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