| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a memory device controller capable of changing easily capacities of physical RAMs allocated respectively in a ROM space and a RAM space controlled by a CPU. <P>SOLUTION: An address signal 20 is decoded to generate an access signal 22 and an access signal 24 in an address decoder 10. The logic sum of the access signal 22 and the access signal 24 is computed to generate a chip enable signal 26 in an OR circuit 12. An address signal 28 is generated to access a RAM 18 from a top address in a descending order based on the address signal 20 in an address generation circuit 14. An address inversion circuit 16 inverts each bit of the address signal 28 to be outputted when the access signal 24 is "logic" 1, and outputted as it is when the access signal 24 is "logic" 0. Reading-out or writing is carried out in the RAM 18 according to an address signal 30 supplied from the address inversion circuit 16 when the chip enable signal 26 is "logic" 1. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
