发明名称 CONFIGURATION FOR GENERATING A CLOCK INCLUDING A DELAY CIRCUIT AND METHOD THEREOF
摘要 <p>A delay locked loop (DLL) employs a gray code (an alternate code) counter as a delay register. Preventing a carry from arising at more than one bit can minimize skipping of delay time (discontinuous skipping thereof) if a metastable state should occur.</p>
申请公布号 KR100516542(B1) 申请公布日期 2005.09.22
申请号 KR20010049022 申请日期 2001.08.14
申请人 发明人
分类号 G11C8/00;G11C11/407;G06F1/10;G11C7/22;G11C11/4076;H03K5/00;H03K5/14;H03K23/64;H03L7/081;H03M7/16;(IPC1-7):G11C8/00 主分类号 G11C8/00
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