发明名称 |
Memory control device, data cache control device, central processing device, storage device control method, data cache control method, and cache control method |
摘要 |
A central processing device includes a plurality of sets of instruction processors that concurrently execute a plurality of threads and primary data cache devices. A secondary cache device is shared by the primary data cache device belonging to different sets. The central processing device also includes a primary data cache unit and a secondary cache unit. The primary data cache unit makes an MI request to the secondary cache unit when a cache line with a matching physical address but a different thread identifier is registered in a cache memory, performs an MO/BI based on the request from the secondary cache unit, and sets a RIM flag of a fetch port. The secondary cache unit makes a request to the primary cache unit to perform the MO/BI when the cache line for which MI request is received is stored in the primary data cache unit by a different thread.
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申请公布号 |
US2005210204(A1) |
申请公布日期 |
2005.09.22 |
申请号 |
US20050123140 |
申请日期 |
2005.05.06 |
申请人 |
FUJITSU LIMITED |
发明人 |
YAMAZAKI IWAO |
分类号 |
G06F12/00;G06F12/08;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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地址 |
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