发明名称 |
High holding voltage ESD protection structure and method |
摘要 |
The holding voltage (the minimum voltage required for operation) of a LVTSCR-like device is increased to a value that is greater than a dc bias on a to-be-protected node. The holding voltage is increased by reducing the size of the p+ emitter defined by the LVTSCR-like device. As a result, the LVTSCR can be utilized to provide ESD protection to power supply pins, having better current capabilities than a GGNMOS and better holding voltage characteristics than a LVTSCR.
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申请公布号 |
US6946690(B1) |
申请公布日期 |
2005.09.20 |
申请号 |
US20010816287 |
申请日期 |
2001.03.21 |
申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
VASHCHENKO VLADISLAV;CONCANNON ANN;HOPPER PETER J. |
分类号 |
H01L27/02;H01L29/74;(IPC1-7):H01L29/74 |
主分类号 |
H01L27/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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