发明名称 |
Nonvolatile memory solution using single-poly pflash technology |
摘要 |
A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.
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申请公布号 |
US2005199936(A1) |
申请公布日期 |
2005.09.15 |
申请号 |
US20040794564 |
申请日期 |
2004.03.05 |
申请人 |
WANG ALEX;CHANG SHANG-DE T.;LIN HAN-CHIH;SHIAU TZENG-HUEI;LIU I-SHENG;LIN HSIEN-WEN |
发明人 |
WANG ALEX;CHANG SHANG-DE T.;LIN HAN-CHIH;SHIAU TZENG-HUEI;LIU I-SHENG;LIN HSIEN-WEN |
分类号 |
H01L21/8247;G11C16/04;H01L27/115;H01L29/423;H01L29/76;H01L29/788;H01L29/792;(IPC1-7):H01L29/76 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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