Identical core testing using dedicated compare and mask circuitry

摘要

Today large system-on-chips (SOC) are designed using predefined circuit functions commonly referred to as cores. In some cases, multiple instances of the same core may be implemented within an SOC to achieve greater functional performance of the SOC. Having multiple cores of the same type in an SOC lends itself to parallel testing of the cores. This disclosure describes an improved core DFT architecture that facilitates parallel testing of same type cores within an SOC.