Technique for combining scan test and memory built-in self test

摘要

Semiconductor devices including logic circuitry and embedded memories may be more efficiently tested in that one or more flip-flops in a scan chain are connected to a control input of an MBIST logic, thereby allowing the control of the MBIST logic during a simultaneous scan test and memory test run. By combining the output of the MBIST logic with the output of the scan chain, fault diagnosis is maintained.