| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a microcomputer capable of flexibly varying setup time and/or hold time, while minimizing the influence of competition between a CPU and a DMA for buses. <P>SOLUTION: An edge detection circuit 10 detects a change (edge) in the input level of a synchronization signal SYN inputted from a synchronization signal input terminal 2. A data latching part 20 latches digital data DD inputted from an external data input terminal 3. An address generating circuit 30 outputs an address signal ADD. A write control part 40 either activates or deactivates a write enable signal WEX for implementing writing in a RAM 90. An arbitration circuit 60 monitors the write control enable signal WEX, a read enable signal RE, and a write enable signal WE to find a cycle where the CPU 80 is not accessing the RAM 90. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
