| 摘要 |
First to fourth gate driver ICs G 1 to G 4 to be connected to a gate line 18 of a drive element 21 are arranged along a side of a liquid crystal display 2. Along a side of the first to four gate driver ICs G 1 to G 4, a FPC 5 for receiving signals is arranged. A first bus line 15 that branches between the first and second gate driver ICs G 1 and G 2 connects gate-low terminals 11 b and 11 a of the first and second gate driver ICs G 1 and G 2, respectively, to the FPC 5 . A second bus line 16 that branches between the third and fourth gate driver ICs G 3 and G 4 connects gate-low terminals 11 b and 11 a of the third and fourth gate driver ICs G 3 and G 4 , respectively, to the FPC 5 . Gate-high terminals 10 b and 10 a, logic terminals 12 b and 12 a, and signal terminals 13 of the second and third gate driver ICs G 2 and G 3 are connected to the FPC 5. Gate-high terminals 10 a and 10 b, logic terminals 12 a and 12 b, and signal terminals 13 of the first and fourth gate driver ICs G 1 and G 4 are connected to corresponding terminals of the second and third gate driver ICs G 2 and G 3.
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