发明名称 JOINING METHOD AND STRUCTURE OF ELECTRONIC COMPONENT
摘要 PROBLEM TO BE SOLVED: To secure the quality and the reliability of a product by preventing wrong effects generated from unhardened portions of an underfill. SOLUTION: On a transparent substrate 1, there is provided an underfill 6 comprising the laminate of a lower-side bonding layer 2 made of a thermosetting resin and an upper-side bonding layer 5 made of an anisotropic conductive boding material having a thermohardening resin, to dispose a semiconductor chip 4 on the underfill 6 and to thermocompressvely bond the chip 4 to the substrate 1 by a pressing heater 7. At this time, portions of the upper-side bonding layer 5 are extruded in the externally side direction of the semiconductor chip 4 to dispose the extruded portions of the upper-side bonding layer 5 on the lower-side bonding layers 2. Also, the opposite portion of the thermohardening resin of the upper-side bonding layer 5 to the rear surface of the semiconductor chip 4 is so hardened as to join the semiconductor chip 4 to the transparent substrate 1 by this hardened portion 5a. Since the extruded portions of the thermohardening resin to the external are disposed on the lower-side bonding layers 2 as unhardened portions 5b, the wrong effects generated from the unhardened portions 5b are so prevented by these lower-side bonding layers 2 as to be able to secure the quality and the reliability of a product. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005252135(A) 申请公布日期 2005.09.15
申请号 JP20040063592 申请日期 2004.03.08
申请人 CASIO COMPUT CO LTD 发明人 HOKARI KAZUSHI
分类号 H05K3/28;H01L21/60;(IPC1-7):H01L21/60 主分类号 H05K3/28
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