发明名称 MULTI-LAYER OVERLAY MEASUREMENT AND CORRECTION TECHNIQUE FOR IC MANUFACTURING
摘要 A system facilitating measurement and correction of overlay between multiple layers of a wafer (402) is disclosed. The system comprises an overlay target (406) that represents overlay between three or more layers of a wafer (402) and a measurement component (408) that determines overlay error existent in the overlay target (406), thereby determining overlay error between the three or more layers of the wafer (402). A control component (410) can be provided to correct overlay error between adjacent and non-adjacent layers, wherein the correction is based at least in part on measurements obtained by the measurement component (408).
申请公布号 WO2005086223(A2) 申请公布日期 2005.09.15
申请号 WO2005US06178 申请日期 2005.02.26
申请人 ADVANCED MICRO DEVICES, INC.;PHAN, KHOI, A.;RANGARAJAN, BHARATH;SINGH, BHANWAR 发明人 PHAN, KHOI, A.;RANGARAJAN, BHARATH;SINGH, BHANWAR
分类号 G01N21/956;G03F7/20;H01L21/66;H01L23/544 主分类号 G01N21/956
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