| 摘要 |
The invention relates to a frequency divider circuit (1) comprising at least one push-pull divider (T1) with an adjustable divider ratio and comprising a converter device (24), which is connected thereto and which converts a clock signal (TS1) output by the push-pull divider (T1) into a single-ended signal. A first and a second single-ended divider (T2, T3) is connected in outgoing circuit to the output of the converter device (24). A feedback path is provided, which is connected to the outputs of the push-pull divider (T1) and of the first and at least second single-ended divider (T2, T3) and which comprises an evaluation circuit (32). This evaluation circuit comprises a first and a second input (321, 322) which are respectively coupled to the first and to the second single-ended divider (T2, T3) whereby enabling a future state of the clock signal output by the respective single-ended divider to be fed to the inputs of the evaluation circuit. The evaluation circuit evaluates states of the clock signals output by the first and second single-ended divider that are reached first by future switching functions. This makes it possible to gain additional time for a push-pull/single-ended conversion of the signal to be divided. |
