发明名称 MULTILAYER SYSTEM AND CLOCK CONTROLLING METHOD
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a multilayer system with lower electric consumption and a clock controlling method for the multilayer system. <P>SOLUTION: The multilayer system executes starting of the other secondary masters 1 by means of one primary master 1 such as a CPU or the like, in which clock signals are always supplied from a clock generator 4. The primary master 1 outputs a starting signal starting the secondary master 1 to the secondary master 1 via a slave 3 correlated with the secondary master 1. The secondary master 1 starts up in response to the starting signal, and outputs a clock request signal requesting supply of a clock signal to the secondary master 1 to the clock generator 4. The clock generator 4 supplies the clock signal to secondary master 1 in response to the clock requesting signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p>
申请公布号 JP2005250650(A) 申请公布日期 2005.09.15
申请号 JP20040057598 申请日期 2004.03.02
申请人 NEC ELECTRONICS CORP 发明人 HOSHI SACHIKO;NARAI KYOICHI
分类号 G06F1/10;G06F1/32;G06F13/00;H04Q7/32;(IPC1-7):G06F1/10 主分类号 G06F1/10
代理机构 代理人
主权项
地址