| 摘要 |
An input buffer circuit is disclosed which is connected to a bus for receiving signals from the bus. The input buffer circuit comprises a first buffer (40, 43) for receiving the signals, the first buffer (40, 43) being operable in a first mode in which the signals are transmitted on the bus (10) at a first frequency, a second buffer (41, 44) for receiving the signals, the second buffer (41, 44) being operable in a second mode in which said signals are transmitted on said bus (10) at a second frequency lower than the first frequency, and means (24) for providing one of an output of the first buffer (40, 43) and an output of the second buffer (41, 44) to an internal circuit. The power consumption of the second buffer (41, 44) during operation thereof is lower than power consumption of the first buffer (40, 43) during operation thereof. A corresponding output buffer circuit is also disclosed. <IMAGE> |
