发明名称 PHASE LOCKED LOOP COMPRISING A VARIABLE DELAY AND A DISCRETE DELAY
摘要 A phase locked loop circuit, for providing an oscillating output signal at an output frequency, comprising: a reference counter; a loop counter; a phase detector having a first input coupled to the reference counter and second input coupled to the loop counter; a voltage controlled oscillator having an input coupled to the output of the phase detector and an output for providing the oscillating output signal; a feedback loop coupling the output of the voltage controlled oscillator to the input of the loop counter; and delay circuitry, including a feedback loop, arranged to introduce a discrete delay into the output of the loop counter and/or the reference counter.
申请公布号 KR20050091035(A) 申请公布日期 2005.09.14
申请号 KR20057012268 申请日期 2005.06.29
申请人 NOKIA CORPORATION 发明人 BEESON PETER
分类号 H03L7/081;H03L7/197;(IPC1-7):H03L7/23;H03L7/18 主分类号 H03L7/081
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