发明名称 |
Method and circuit for precise timing of signals in an embedded DRAM array |
摘要 |
A method and circuit for timing the start of a precharge period in an eDRAM. The circuit including: a delayed lock loop circuit for receiving a clock signal and generating a control signal for adjusting an internal delay of the clock signal; and means for generating a delayed clock signal in response to the control signal. The means for generating the delayed clock signal is a multiple stage delay circuit, each stage of the multiple delay stage circuit connected in series and each stage individually responsive to the control signal.
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申请公布号 |
US6944090(B2) |
申请公布日期 |
2005.09.13 |
申请号 |
US20030604184 |
申请日期 |
2003.06.30 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ANAND DARREN L.;FIFIELD JOHN A.;PILO HAROLD |
分类号 |
G11C29/02;(IPC1-7):G11C8/00 |
主分类号 |
G11C29/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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