Phase error cancellation circuit and method for fractional frequency dividers and circuits incorporating same

摘要

A frequency divider circuit ( 11 ) has an input port for an input signal (F_o) to be divided, an output port for a divided signal (F_DIV), and means ( 12-19 ) for providing a variable division-ratio control signal (N+C) and a residual quantization error signal (R), applying the variable division ratio control signal (N+C) to a control port of the frequency divider, and using the residual quantization error signal (R) to cancel phase error in the divided signal. Both the variable division ratio control signal (N+C) and the residual quantization error signal (R) are dithered.