发明名称 |
Data transfer control circuit with terminal sharing |
摘要 |
A DMA controller including a request queue for holding DMA transfer requests clears only the request queue without executing unnecessary DMA transfers and provides information about the states of the queue. A DMA controller is configured to enable data transfer control with respect to plural channels and includes a request queue capable of holding the identification information of channels concerned in plural data transfer requests, wherein the states of the request queue can be outputted and information held in the request queue can be cleared.
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申请公布号 |
US6944686(B2) |
申请公布日期 |
2005.09.13 |
申请号 |
US20020255024 |
申请日期 |
2002.09.26 |
申请人 |
HITACHI ULSI SYSTEMS CO., LTD. |
发明人 |
NARUSE TAKANOBU;YOSHIOKA SHINICHI;NAKAGAWA NORIO |
分类号 |
G06F13/28;(IPC1-7):G06F13/28 |
主分类号 |
G06F13/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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