发明名称 Delay locked loop and locking method thereof
摘要 The present invention provides a delay locked loop of a semiconductor memory device for preventing a stuck fail. The DLL of the present invention includes: a buffer for outputting a first clock corresponding to an in-phase of an external clock and outputting a second clock corresponding to an out-of-phase of the external clock; a phase comparator for outputting a control signal to increase/decrease a delay amount after comparing the first clock with a phase of a feedback clock; a shift register for outputting a shift signal in accordance with the control signal; a multiplexing unit for selecting one between the first and the second clocks by using the output of the phase comparator and the output of the shift register.
申请公布号 US6943602(B1) 申请公布日期 2005.09.13
申请号 US20040026970 申请日期 2004.12.30
申请人 HYNIX SEMICONDUCTOR, INC. 发明人 LEE HYUN-WOO
分类号 H03L7/06;(IPC1-7):H03L7/06 主分类号 H03L7/06
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