发明名称 |
Variable fixed multipliers using memory blocks |
摘要 |
A programmable logic device includes at least one RAM block generating a first multi-bit calculation result which may, but does not necessarily, involve a multiplication of two operands. A shift operation is driven by a second multi-bit calculation result shifts the second multi-bit calculation result by at least one bit to generate a shifted second multi-bit calculation result. A multi-bit adder coupled to the at least one RAM block adds the shifted second multi-bit calculation result to the first multi-bit calculation result.
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申请公布号 |
US6943579(B1) |
申请公布日期 |
2005.09.13 |
申请号 |
US20030668449 |
申请日期 |
2003.09.22 |
申请人 |
ALTERA CORPORATION |
发明人 |
HAZANCHUK ASHER;ESPOSITO BENJAMIN |
分类号 |
G06F7/42;G06F7/523;H03K19/177;(IPC1-7):G06F7/42 |
主分类号 |
G06F7/42 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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