发明名称 |
Design method and system for achieving a minimum machine cycle for semiconductor integrated circuits |
摘要 |
Each flip-flop-to-flip-flop path delay and a target machine cycle obtained in the stages of physical design and packaging design are used as input, and with respect to a path in which the path delay is not less than the target machine cycle, a closed loop including the path is extracted, and the timing of a clock signal of each flip-flop is adjusted so as to permit data transmission along the closed loop in a required cycle-number. At this time, a path along which data transmission is impossible in the target machine cycle or a closed loop including the path is listed in order to be modified. As methods of supplying a clock signal to each flip-flop, a plurality of methods different in the adjustable range of clock timing are combined and used.
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申请公布号 |
US6944840(B2) |
申请公布日期 |
2005.09.13 |
申请号 |
US20020073312 |
申请日期 |
2002.02.13 |
申请人 |
HITACHI SOFTWARE ENGINEERING CO., LTD. |
发明人 |
SASAKI TETSUO;NAGAO YOUSUKE;ISHII TATSUKI;MATSUMOTO ITARU |
分类号 |
G04F8/00;G04F10/00;G06F17/50;H01L21/82;(IPC1-7):G06F17/50 |
主分类号 |
G04F8/00 |
代理机构 |
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主权项 |
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地址 |
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