| 摘要 |
A phase detection system is used in particular in a Delay-Locked Loop (DLL) to generate, as a function of phase differences of different signals ( 1, 2, 3 ), at least one control signal for changing the phase delay of phase delay elements ( 8, 9 ) in order to obtain a defined phase delay between the signals ( 1, 2, 3 ). For this purpose, an up signal for increasing the phase delay and a down signal for reducing the phase delay are advantageously generated, both of which signals act on a charge pump ( 21 ) the output signal of which can be used to control the phase delay elements ( 8, 9 ). To be able to control even very small phase differences, the up signal and the down signal are generated in such a way that in the steady oscillating state they simultaneously adopt their active switching state for a certain duration during each period. To obtain good control performance of the phase delay of the two phase delay elements ( 8, 9 ), in particular even at high frequencies, the up signal and the down signal are generated according to the invention in such a way that in the steady oscillating state, i.e. when the phase delay of both phase delay elements ( 8, 9 ) corresponds to the reference phase delay, they each adopt their active switching state for at least one-quarter of the period duration of an input signal ( 1 ). The up signal and the down signal are preferably generated by a circuit arrangement of logic gates ( 10-19, 22-32 ).
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