| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To enable generating a DLL clock compensated by several clocks. <P>SOLUTION: This circuit has a dummy delay (dummy delay circuit 200) corresponding to internal clock delay for an external clock, a variable delay adding circuit having a coarse delay circuit 400 and a fine delay circuit 500 adjusting delay quantity by a delay quantity adjusting signal, and a phase comparing circuit 300 comparing the internal clock with a delay clock inputted through the variable delay circuit and dummy delay and outputting a delay quantity adjusting signal to the variable delay adding circuit. A first signal set to logic "1" is inputted to the variable delay adding circuit through dummy delay during one clock period of the internal clock as an initialization mode at the time of burst start, a continuous time of the logic "1" of the first signal is detected by finish of the first clock period of the internal clock by the variable delay adding circuit , delay quantity of the variable delay adding circuit is set initially by setting delay quantity of the course delay circuit based on the continuous time. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
