| 摘要 |
This invention details a process whereby state assignments and decode logic of a state machine can be mapped to an optimized representation. Optimization may constitute a reduction of gates, an increase of speed, or a reduction of power utilization. Optimization is particularly important when implementing timing systems. A timing system is one of many possible configurations of a state machine. Design engineers are under extreme time pressures; an optimal implementation requires an extensive amount of time. What typically is implemented is the quickest possible solution. Current HDL synthesizers are constrained by what they are given, so the most optimal solution is rarely achieved. A program can be created to examine a plethora of different implementation possibilities and choose the one that creates the least amount of gates. Therefore, not only does the designer save a great deal of time, the design is also highly optimized.
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