发明名称 |
CHARGE PUMP PHASE LOCKED LOOP WITH IMPROVED POWER SUPPLY REJECTION |
摘要 |
A phase lock loop circuit ( 60 ) has a phase frequency detector ( 62 ), a charge pump ( 64 ), an active filter ( 87 ) and a voltage-controlled oscillator ( 100 ). The phase detector generates signals responsive to reference signal F<SUB>R </SUB>and VCO output signal F<SUB>V</SUB>. A charge pump generates a voltage at the input of a first transmission gate ( 76 ) according to the values of the phase detector signals. A predetermined voltage is generated at the input of a second transmission gate ( 112 ). When the transmission gates ( 76, 110 ) are closed (low impedance) the charge pump may sink or source current to the inverting input of the operational amplifier ( 86 ) of the active filter 86 and the predetermined voltage is applied to the non-inverting input. When the transmission gates are open (high impedance state) the inverting input is electrically isolated from the node and the non-inverting output is isolated from the power supply.
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申请公布号 |
US2005195002(A1) |
申请公布日期 |
2005.09.08 |
申请号 |
US20040793367 |
申请日期 |
2004.03.03 |
申请人 |
PUCCIO GIANNI;BISANTI BIAGIO;CIPRIANI STEFANO |
发明人 |
PUCCIO GIANNI;BISANTI BIAGIO;CIPRIANI STEFANO |
分类号 |
H03L7/00;H03L7/06;H03L7/089;H03L7/18;(IPC1-7):H03L7/00 |
主分类号 |
H03L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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