Adder-subtracter circuit

摘要

The present invention relates to an adder-subtracter circuit being adapted to process two binary input numbers in order to generate the sum or the difference of the two processed numbers depending on the state of a subtract input signal. Furthermore the circuit has the capability to feed back the result of the processing to itself in order to process one input number together with the result of a previous processing instead of the second binary number. The circuit uses a subtract logic circuit receiving the second binary number and the subtract input signal for XORing each bit the second binary number and the subtract signal to generate an intermediate second binary number (d 2' ), a select logic circuit receiving the intermediate second binary number and a feedback binary number (c) to output the second binary number (d 2' ) or the feedback binary number (c) dependent on the state of the bypass signal; a main logic circuit receiving the output of the select logic circuit and the first binary number (d 1 ) for processing each pair of respective bits from the first binary number (d 1 ) and the output of the select logic circuit to generate a set of intermediate carry terms (p) and a set of summation carry terms (g) relative to bit positions of a sum of the first binary number (d 1 ) and the output of the select logic circuit, output logic gates for combining the set of the intermediate carry terms (p) with the set of the summation carry terms (g) from the main logic circuit to generate an output (r) related to the result of the processing of the circuit; and a feedback logic circuit receiving the set of the intermediate carry terms (p), the set of the summation carry terms (g) and the subtract signal for processing the received sets to generate a set of intermediate feedback terms (c') by XORing each intermediate carry term (p) with the inverse of the subtract signal and to generate the feedback binary number (c) by bitwise XORing each intermediate feedback term (c') with the respective summation carry term (g). With this arrangement the processing paths for the intermediate carry terms (p) and the summation carry terms (g) can be modified such that the overall gate delay in the circuit can be reduced and the maximum frequency of instruction executions can be increased.