发明名称 |
Method and apparatus for a variable memory enable deassertion wait time |
摘要 |
An integrated circuit designed to be coupled to a suspendable memory, the integrated circuit comprising a memory enable deassertion delay (MEDD) logic setting a wait period for the deassertion of a memory enable signal after completion of a memory operation. The wait period is chosen for a preferred latency versus power savings tradeoff.
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申请公布号 |
US2005198542(A1) |
申请公布日期 |
2005.09.08 |
申请号 |
US20040796366 |
申请日期 |
2004.03.08 |
申请人 |
FREKER DAVID;MUKKER ANOOP;BOGIN ZOHAR |
发明人 |
FREKER DAVID;MUKKER ANOOP;BOGIN ZOHAR |
分类号 |
G06F1/26;G06F1/32;(IPC1-7):G06F1/32 |
主分类号 |
G06F1/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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