| 摘要 |
One embodiment of the invention provides a semiconductor memory apparatus comprising: a multiplicity of memory cells which are arranged in the manner of a matrix at least in regions, a multiplicity of address contacts for receiving a row address and/or column address for at least one memory cell, at least one address decoder for decoding the row and/or column addresses, and a descrambling device which is arranged in the electrical signal path between the address contacts and the address decoder. The descrambling device comprises address inputs for accepting input address bits of an input address which are received via the address contacts and address outputs for outputting output address bits of an output address to the address decoder. In a descrambling mode, the descrambling device is designed to allocate an output address bit explicitly to each input address bit of a received, scrambled row and/or column address such that the output address is the same as the unscrambled address. The descrambling device further comprises, for each output address bit, an allocation device for allocating the output address bit to a corresponding input address bit. The allocation devices of all output address bits may have the same design.
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