| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To improve processing efficiency by performing variable length decoding processing as processor-oriented processing without requiring any dedicated device. <P>SOLUTION: This variable length decoding device comprises a memory 101, a buffer register 103 for storing data loaded from the memory 101, and an address register 102 for storing the number M of data which are referred to in the buffer register, at a lower-bit side and storing an access address to the memory at a higher-bit side. When extracting data to be presently referred to for variable length decoding from the data loaded from the memory by the access address, the buffer register extracts the data to be referred to by a data shift operation using the number of referred-to data and the number of data to be presently referred to and updates the number of data which are referred to in the address register, by adding the number of data to be presently referred to, to the above number of data with the extraction of the data. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
