| 摘要 |
A method of synthesizing a clock tree for reducing peak power in an integrated circuit design includes partitioning a circuit design into a set of memory cells and a set of non-memory cells, partitioning the set of memory cells into segments, constructing a first clock tree having a first root vertex with a corresponding initial skew for each of the segments, constructing a second clock tree having a second root vertex with a corresponding initial skew for the set of non-memory cells, delay balancing the first root vertex and the second vertex clock tree, and inserting a clock buffer at a midpoint between the first root vertex and the second root vertex.
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