发明名称 |
Method of wafer level chip scale packaging |
摘要 |
The invention includes a method of wafer level chip scale packaging including providing a semiconductor device having a silicon based substrate with discrete devices defined therein and a contact pad near an upper surface thereof, a passivation layer overlying the silicon based substrate and the contact pad, and the passivation layer having an opening therein exposing at least a portion of the contact pad, and a redistribution trace electrically connected to the contact pad near a first end and having a second end of spaced a distance from the contact pad. Forming an encapsulation layer over the semiconductor device including the redistribution trace. Forming an opening in the encapsulation layer down to the redistribution trace. Forming a contact post in the opening in the encapsulation layer, and the contact post having a first end electrically connected to the redistribution trace and a second exposed end. Forming an electrically conductive bump on the semiconductor device and in electrical contact with the contact post. |
申请公布号 |
US6939789(B2) |
申请公布日期 |
2005.09.06 |
申请号 |
US20020144074 |
申请日期 |
2002.05.13 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
HUANG CHENDER;TSAO PEI-HAW;WANG JONES;CHEN KEN |
分类号 |
H01L23/31;H01L23/485;(IPC1-7):H01L21/44 |
主分类号 |
H01L23/31 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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